A General Multi Microprocessor Interconnection Mechanism for Non Numeric Process

Cover A General Multi Microprocessor Interconnection Mechanism for Non Numeric Process
A General Multi Microprocessor Interconnection Mechanism for Non Numeric Process
Hoo Min D Toong
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r/user mode s a valuable protection eparate syste processor an "atomic" a vectored ating system uction set fully reloca ide, and man mechan isms, ng modes eparat featur of c m/user has test a int suppor in table y h igh inc and r ion in e. It er tain stack an nd set er rupt The eludes code, level lud ing egular The number o and can digits, 1 as opera string ha future operation improved . (assuming ns .
processor fe f large gene handle bits 6 bit words, nds. There a ndling as a xpansion ro Opera
...tion The short suf f ic lent atures a significant ral purpose registers, , 8 bit bytes, BCD and 32 bit long words re also provisions for stream of bytes, and om for floating point al speed has also been est execution time ly fast memory) is 500 Most of the above processor features would obviously be very useful in a multiple microprocessor environment. However, the problem of interconnection remains to be solved before the features will have any value in the area of MMPS.
3. 1 Microprocessor Timing The MC68000 bus utilization depends on the instruction and data fetching process.


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