Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory Paralle

Susan Dickey

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[15]).
For any given state of technology, packaging constraints do not determine a unique design for the network. For the same number of pins per chip, it is possible to replace 2x2 switches by kxk switches, time multiplexing each pin by a factor of k/2. Dividing a message into more packets may or may not involve an increase in cycle time, depending on the nature of the detailed VLSI design. Breaking up parts of the address or the data into different packets will increase the internal complexit...y required to handle matching and addition, but fewer bits per packet will shorten certain global control lines. The increased logic to perform kxk switching rather than 2x2 switching is likely to increase cycle time, but possibly not by a significant amount. In the following subsection, we present performance analyses of various networks in order to indicate the tradeoffs involved.
3. 2. Network performance analysis A particular configuration is characterized by the values of the following parameters: k The size of the switch.

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