Networks And Algorithms for Very Large Scale Parallel Computation
Networks And Algorithms for Very Large Scale Parallel Computation
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For the latter system, if each processor randomly generates one memory reference per microsecond, a 3. 2 gigacycle memory bandwidth is achieved. . '- " n The Burroughs architecture employs 9 stages of 256 simple "... . I . T £ a a e ■ two-input two-output switches to perform exchanges and effects the (inverse) shuffle maps by wiring between stages. This leads to the familiar interconnection network of Lawrie [75], illustrated (for 16 processors) in Fig. 1.
In such a network P = 2»*D PEs communi...cate. To describe the network in detail, we shall suppose that the PEs are numbered using D-bit identifiers whose values range from to P-1, and that the binary representation of an identifier x is written xD... X1. Then the network consists of D stages of 2 X 2 switches with adjacent stages connected via the inverse of the shuffle map. The PEs are directly connected to the first stage of switches and are connected via the inverse shuffle to the last stage of switches. Each of the P/2 2X2 switches constituting a single network stage can separately transmit data in one of two modes, "straight", in which its left-hand top and bottom terminals are connected to the right-hand top and bottom terminals respectively, and "crossed", in which its left-hand top and bottom terminals are connected to the right-hand bottom and Page ^^ top terminals respectively (see Fig.
What to read after Networks And Algorithms for Very Large Scale Parallel Computation?
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To quickly assess the difficulty of the text, read a short excerpt:
For the latter system, if each processor randomly generates one memory reference per microsecond, a 3. 2 gigacycle memory bandwidth is achieved. . '- " n The Burroughs architecture employs 9 stages of 256 simple "... . I . T £ a a e ■ two-input two-output switches to perform exchanges and effects the (inverse) shuffle maps by wiring between stages. This leads to the familiar interconnection network of Lawrie [75], illustrated (for 16 processors) in Fig. 1.
In such a network P = 2»*D PEs communi...cate. To describe the network in detail, we shall suppose that the PEs are numbered using D-bit identifiers whose values range from to P-1, and that the binary representation of an identifier x is written xD... X1. Then the network consists of D stages of 2 X 2 switches with adjacent stages connected via the inverse of the shuffle map. The PEs are directly connected to the first stage of switches and are connected via the inverse shuffle to the last stage of switches. Each of the P/2 2X2 switches constituting a single network stage can separately transmit data in one of two modes, "straight", in which its left-hand top and bottom terminals are connected to the right-hand top and bottom terminals respectively, and "crossed", in which its left-hand top and bottom terminals are connected to the right-hand bottom and Page ^^ top terminals respectively (see Fig.
What to read after Networks And Algorithms for Very Large Scale Parallel Computation?
You can find similar books in the "Read Also" column, or choose other free books by Allan Gottlieb to read onlineMoreLess
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