Queuing Delaymodeling for Multistage Interconnection Multiprocessor Networks
Queuing Delaymodeling for Multistage Interconnection Multiprocessor Networks
Paul G Spirakis
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Report #44, 1982. [KS, 83] C. Kruskal and Snir, M. , "The Performance of Multistage Interconnection Networks for Multiprocessors, " IEEE Trans. Computing, Dec. 1983. [KSW, 84] C. Kruskal, M. Snir and A. Weiss, "On the Distribution of Delays in Buffered Multistage Interconnection Networks for Uniform and Nonuniform Traffic", to appear. [M, 84] McAuliffe, K. , "Ultracomputer Cache Modeling, " NYU Ph. D. Thesis, 1984, unpublished. [PA, 81] J. A. Patel, "Performance of processor-memory interconnect...ions for multiprocessors, " IEEE Trans. Comp. C-30, 1981. A-1 Appendix Simulations conducted by [KS, 83] and additional simulations we conducted, validate Theorems 1 and 2. The delays (obtained through simulation) at subsequent network stages are all very close to the delays of the first stage and do not differ among them. Slight dlffernces among mean delays for various stages are not statistically significant. Table 1 Simulation of 512 Processors (9 stages) of 2 x 2 switches, buffer size = 8, pnl = processor network interface, mnl = memory network Interface 1 p = 0.
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