Toward a Fully Integrated Vlsi Cad System From Custom to Fully Automatic

Yongtao You

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CLK. NCLK) in bit T, CLK, nCLK; i out bit Q; state bit S = 0; il ((T == 1) tk (CLK == 1)) if (S == 0) S = 1; else if (S == 1) S = 0; else S = X; Q = S; It is easy to see that the name of our T flip-flop is TFLIP, and it has a control line T and two clocks CLK and nCLK as inputs; and Q as output.
Having our T flip-flop as a subcell, the second version of out counter may contains more information on how the counter is constructed: cell CTR; /* a binary counter */ bit T; bit CLK, nCLK; bit C [4] ;... use TFLIP [4]; simulate C; /♦ version 2 •/ CTRCT, CLK. NCLK) in bit T, CLK, nCLK; ■C out bit C [4] ; state unsigned count = 0; bit carry [33; carry [0] = (T ft C[0]); carry [1] = (T ft C[0] ft C[l] ) ; carry [2] = (T ft C[0] ft C[l] ft C[2]); map TFLIP [0] [0] (T. CLK. NCLK; C[0]); map TFLIP [0][1] (carry[0], CLK. NCLK; C[l]) map TFLIP[0][2] (carryCl], CLK, nCLK; CC2]) map TFLIP [0] [3] (carry [2], CLK, nCLK; CC3]) 35 Again, if the circuit was larger, you should simulate it to find out any possible error in the specification or in the interconnection.

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